Rajeev Barua's Publications

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Rajeev Barua

Associate Professor

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	Refereed Journals: 1) Kapil Anand and Rajeev Barua. “Instruction Cache Locking for Improving Embedded Systems Performance”. To appear in the ACM Transactions on Embedded Computing Systems (TECS) (Accepted September 2014). 2) Aparna Kotha, Kapil Anand, Timothy Creech, Khaled ElWazeer, Matthew Smithson, Greeshma Yellareddy, and Rajeev Barua. “Affine Parallelization using Dependence and Cache analysis in a Binary Rewriter”. To appear in the IEEE Transactions on Parallel and Distributed Systems (TPDS). (Accepted July 2014). 3) Lazy Scheduling: A Run-Time Adaptive Scheduler for Declarative Parallelism. Alexandros Tzannes, George Caragea, Uzi Vishkin and Rajeev Barua. In ACM Transactions on Programming Languages and Systems (TOPLAS), 36(3), September 2014. 4) Implementation and Performance Evaluation of a Distributed Conjugate Gradient Method in a Cloud Computing Environment. Leila Fayez and Rajeev Barua. In the Journal on Software: Practice and Experience (SPE), John Wiley and Sons, Ltd. February, 2012. doi: 10.1002/spe.2112. 5) MemSafe: Ensuring the Spatial and Temporal Memory Safety of C at Runtime. Matthew Simpson and Rajeev Barua. In the Journal on Software: Practice and Experience (SPE), John Wiley and Sons, February 2012. doi: 10.1002/spe.2105 6) Resource-Aware Compiler Prefetching for Fine-Grained Many-Cores. George Caragea, Alexandros Tzannes, Fuat Keceli, Rajeev Barua and Uzi Vishkin. In the International Journal of Parallel Programming (IJPP), 39(5), pp 615-638, Springer Netherlands, ISSN: 0885-7458, February 28, 2011. 7) Memory Allocation for Embedded Systems with a Compile-Time-Unknown Scratch-Pad Size. Nghi Nguyen, Angel Dominguez, and Rajeev Barua. In ACM Transactions on Embedded Computing Systems (TECS), 8(3), pp 1-32, April 2009. 8) MTSS: Multi Task Stack Sharing for Embedded Systems Bhuvan Middha, Matthew Simpson and Rajeev Barua In ACM Transactions on Embedded Computing Systems (TECS), 7(4), Article 46, pp 1-37, July 2008. 9) Memory Overflow Protection for Embedded Systems using Run-time Checks, Reuse and Compression. by Surupa Biswas, Thomas Carley, Matthew Simpson, Bhuvan Middha and Rajeev Barua. In ACM Transactions on Embedded Computing Systems (TECS), 5(4), pp 719 - 752, Nov 2006. 10) Dynamic Allocation for Scratch-Pad Memory using Compile-Time Decisions. by Sumesh Udayakumaran, Angel Dominguez and Rajeev Barua. In ACM Transactions on Embedded Computing Systems (TECS), 5(2), pp 472-511, May 2006. 11) Heap Data Allocation to Scratch-Pad Memory in Embedded Systems. by Angel Dominguez, Sumesh Udayakumaran and Rajeev Barua. In Journal of Embedded Computing, Vol 1, Number 4, pp 521-540, 2005, IOS Press, Amsterdam, The Netherlands. 12) Reducing Code Size in VLIW Instruction Scheduling. by Steve Haga, Yi Zhang, Andrew Webber and Rajeev Barua. In Journal of Embedded Computing, Volume 1, Number 3, 2005, IOS Press, Amsterdam, The Netherlands. 13) Dynamic Functional Unit Assignment for Low Power by Steve Haga, Natasha Reeves, Rajeev Barua and Diana Marculescu. In Journal of Supercomputing, 31(1), pp 47-62, Kluwer Academic Publishers, January 2005. 14) Execution History Guided Instruction Prefetching by Zhang Yi, Steve Haga and Rajeev Barua. In Journal of Supercomputing, 27(2), pp 129-147, February 2004. Kluwer Academic Publishers. 15) An Optimal Memory Allocation Scheme for Scratch-Pad Based Embedded Systems by O. Avissar, R. Barua and D. Stewart. In ACM Transactions on Embedded Computing Systems (TECS), 1(1), pp. 6-26, November 2002. 16) Compiler Support for Scalable and Efficient Memory Systems, R. Barua, W. Lee, S. Amarasinghe and A. Agarwal. IEEE Transactions on Computers, Special Issue on Memory Systems, Nov 2001. 17) Baring it all to the software. by Elliot Waingold, Michael Taylor, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Srikrishna Devabhaktuni, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, and Anant Agarwal IEEE Computer, September 1997, pp. 86-93. Refereed Conferences: 1) Kyungjin Yoo and Rajeev Barua. “Recovery of Object Oriented Features from C++ Binaries.” In Proceedings of the 21st Asia-Pacific Software Engineering Conference (APSEC), Jeju, Korea, December 1-4, 2014. 2) Aroon Sharma, Rajeev Barua, Michael Ferguson, Darren Smith, and Joshua Koehler. “Affine Loop Optimization Based On Modulo Unrolling in Chapel.” In Proceedings of the 8th ACM International Conference on Partitioned Global Address Space Programming Models (PGAS), Eugene, Oregon, October 7-10, 2014. 3) Aparna Kotha, Kapil Anand, Timothy Creech, Khaled Elwazeer, Matthew Smithson and Rajeev Barua. “Affine Parallelization of Loops with Run-time Dependent Bounds from Binaries.” In Proceedings of the 23rd ETAPS European Symposium on Programming (ESOP), Grenoble, France, April 7-11, 2014. 4) Timothy Creech, Aparna Kotha, and Rajeev Barua. “Efficient Multiprogramming for Multicores with SCAF.” In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Davis, California, December 7-11, 2013. 5) Matthew Smithson, Khaled Elwazeer, Kapil Anand, Aparna Kotha, and Rajeev Barua. “Static Binary Rewriting without Supplemental Information : Overcoming the tradeoff between coverage and correctness.” In Proceedings of the 20th Working Conference on Reverse Engineering (WCRE), Koblenz, Germany, October 14-17, 2013. 6) Kapil Anand, Khaled Elwazeer, Aparna Kotha, Matthew Smithson, Rajeev Barua and Angelos Keromytis. “An Accurate Stack Memory Abstraction and Symbolic Analysis Framework for Executables.” In Proceedings of the 29th International Conference on Software Maintenance (ICSM '13). 7) Khaled ElWazeer, Kapil Anand, Aparna Kotha, Matt Smithson, and Rajeev Barua, "Scalable Variable and Data Type Detection in a Binary Rewriter." In Proceedings of the 34th ACM SIGPLAN conference on Programming Language Design and Implementation (PLDI), 2013. 8) Kapil Anand, Aparna Kotha, Khaled ElWazeer, Matt Smithson, Jim Gruen, Nathan Giles, and Rajeev Barua, "A compiler-level intermediate representation based binary analysis and rewriting system," In Proceedings of the 8th European Conference on Computer Systems (Eurosys), 2013. 9) Improving Run-Time Scheduling for General-Purpose Parallel Code. Alexandros Tzannes, Rajeev Barua, and Uzi Vishkin. In Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques (PACT '11). IEEE Computer Society, Washington, DC. (Won best paper among ACM conducted Student research competition at PACT.) 10) Retrofitting Security in COTS Software with Binary Rewriting. by Padraig O'Sullivan, Kapil Anand, Aparna Kotha, Matthew Smithson, Rajeev Barua and Angelos D. Keromytis. Proceedings of the 26th IFIP International Information Security Conference (IFIP SEC). June 7-9, 2011, Lucerne, Switzerland. (12 pages) 11) Toolchain for Programming, Simulating and Studying the XMT Many-Core Architecture. by Fuat Keceli, Alexandros Tzannes, George C. Caragea, Rajeev Barua, Uzi Vishkin. Proceedings of the 16th International Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS), May 20, 2011. Anchorage, Alaska. (10 pages) 12) Automatic parallelization in a binary rewriter. by Aparna Kotha, Kapil Anand, Matthew Smithson, Greeshma Yellareddy, and Rajeev Barua. Proceedings of the 43rd International ACM/IEEE symposium on Microarchitecture (MICRO). December 4-8, 2010, Atlanta, Georgia. (11 pages) 13) MemSafe: Ensuring the Spatial and Temporal Memory Safety of C at Runtime. by Matthew Simpson and Rajeev Barua. Proceedings of the 10th IEEE Working Conference on Source Code Analysis and Manipulation (SCAM). September 12–13, 2010. Timişoara, Romania. (10 pages) 14) Resource-Aware Compiler Prefetching for Many-Cores. by George Caragea, Alexandros Tzannes, Rajeev Barua and Uzi Vishkin. Proceedings of the Ninth International Symposium on Parallel and Distributed Computing (ISPDC). July7-9, 2010. Istanbul, Turkey (8 pages) 15) Lazy Binary-Splitting: A Run-Time Adaptive Dynamic Parallel Scheduler. by Alexandros Tzannes, George Caragea, Uzi Vishkin and Rajeev Barua. Proceedings of the 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP). January 9–14, 2010, Bangalore, India (11 pages) 16) Instruction Cache Locking inside a Binary Rewriter. by Kapil Anand and Rajeev Barua. Proceedings of the ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Grenoble, France, October 11-16, 2009. (10 pages) 17) Scratch-Pad Memory Allocation without Compiler Supports for Java Applications By Nghi Nguyen, Angel Dominguez and Rajeev Barua. In Proceedings of the ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Salzburg, Austria, October 1-3, 2007. (10 pages) 18) Recursive Function Allocation to Scratch-Pad Memory for Embedded Systems By Angel Dominguez, Nghi Nguyen and Rajeev Barua. In Proceedings of the ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Salzburg, Austria, October 1-3, 2007. (10 pages) 19) An Integrated Scratch-Pad Allocator for Affine and Non-affine Codes. By Sumesh Udayakumaran and Rajeev Barua. In Proceedings of International Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 6-10, 2006. (6 pages) 20) Segment Protection for Embedded Systems Using Run-time Checks By Matthew Simpson, Bhuvan Middha and Rajeev Barua. Proceedings of the ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), San Francisco, CA, September 25-27, 2005. 21) Memory Allocation for Embedded Systems with a Compile-Time-Unknown Scratch-Pad Size. By Nghi Nguyen, Angel Dominguez and Rajeev Barua. Proceedings of the ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), San Francisco, CA, September 25-27, 2005. 22) MTSS: Multi Task Stack Sharing for Embedded Systems. By Bhuvan Middha, Matthew Simpson and Rajeev Barua. Proceedings of the ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), San Francisco, CA, September 25-27, 2005. 23) Memory Overflow Protection for Embedded Systems using Run-time Checks, Reuse and Compression By Surupa Biswas, Matthew Simpson and Rajeev Barua. Proceedings of the ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems(CASES), Washington, DC, September 23-25, 2004. 24) Contention-Free Periodic Task Scheduler Medium Access Control in Wireless Sensor / Actuator Networks. By Tom Carley, Musa Ba, Rajeev Barua and Dave Stewart. Proceedings of The 24th IEEE Real-Time Systems Symposium (RTSS), Cancun, Mexico, December 3-5, 2003. 25) Compiler-Decided Dynamic Memory Allocation for Scratch-Pad Based Embedded Systems. By Sumesh Udayakumaran and Rajeev Barua. Proceedings of the ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems(CASES), San Jose, CA, October 30-November 1, 2003. 26) Dynamic Functional Unit Assignment for Low Power. By S. Haga, N. Reeves and R. Barua. Proceedings of International Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 3-7, 2003. 27) Execution History Guided Instruction Prefetching. o by Zhang Yi, Steve Haga and Rajeev Barua. Proceedings of the Sixteenth ACM Int'l Conference on Supercomputing (ICS), New York City, NY, June, 2002. 28) Compiler-directed Customization of ASIP Cores. o by T.V.K Gupta, Roberto Ko and Rajeev Barua. Proceedings of Tenth ACM/IEEE Int'l Symposium on Hardware/Software Codesign (CODES), Estes Park, CO, May, 2002. 29) Heterogeneous Memory Management for Embedded Systems, o O. Avissar, R. Barua and D. Stewart. Proceedings of the ACM 2nd Int'l Conf. on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), Atlanta, GA, November 2001. 30) Maps: A Compiler-Managed Memory System for Raw Machines, o by Rajeev Barua, Walter Lee, Saman Amarasinghe and Anant Agarwal. Proceedings of the Twenty-Sixth International Symposium on Computer Architecture (ISCA), Atlanta, GA, June, 1999. pp 4-15. 31) Memory Bank Disambiguation using Modulo Unrolling for Raw Machines, o by Rajeev Barua, Walter Lee, Saman Amarasinghe and Anant Agarwal. Proceedings of the ACM/IEEE Fifth International Conference on High-Performance Computing (HiPC), December, 1998. pp 212-220. 32) Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine, o by W. Lee, R. Barua, D. Srikrishna, J. Babb, V. Sarkar, and S. Amarasinghe. Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems(ASPLOS), San Jose, CA, October, 1998. pp 46-57. 33) Parallelizing Applications into Silicon o by Jonathan Babb, Martin Rinard, Andras Moritz, Walter Lee, Matthew Frank, Rajeev Barua, and Saman Amarasinghe Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines '99 (FCCM '99), Napa Valley, CA, April 1999, pp 70-80. (Selected among the most significant 25 papers in the first 20 years of the International IEEE Symposium on Field-Programmable Custom Computing Machines.) 34) The Raw Compiler Project, o by Anant Agarwal, Saman Amarasinghe, Rajeev Barua, Matthew Frank, Walter Lee, Vivek Sarkar, Devabhaktuni Srikrishna and Michael Taylor. Proceedings of the Second SUIF compiler workshop, Stanford, CA, August 21-23, 1997. 35) The RAW Benchmark Suite: Computation Structures for General Purpose Computing, o by Jonathan Babb, Matthew Frank, Elliot Waingold, Rajeev Barua, Michael Taylor, Jang Kim, Srikrishna Devabhaktuni, Peter Finch, and Anant Agarwal Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) , Napa Valley, CA, April 1997, pp 134-144. 36) The Sensitivity of Communication Mechanisms to Bandwidth and Latency, o by Frederic T. Chong, Rajeev Barua, Fredrik Dahlgren, John D. Kubiatowitz, and Anant Agarwal. Proceedings of 4th Int'l Symposium on High Performance Computer Architecture (HPCA), Las Vegas, NV, Feb 1-4, 1998. 37) Communication-Minimal Partitioning of Parallel Loops and Data Arrays for Cache-Coherent Distributed-Memory Multiprocessors, o by Rajeev Barua, David Kranz and Anant Agarwal. Proceedings of Symposium on Languages and Compilers for Parallel Computing (LCPC), August 1996. Springer Verlag, Berlin, Germany. Refereed Workshops: 1) EPIC Instruction Scheduling Based on Optimal Approaches. o by Steve Haga and Rajeev Barua. 1st Annual Workshop on Explicitly Parallel Instruction Computing Architectures and Compiler Technology (EPIC), Austin, TX, December, 2001. Other Publications: 1) Analysis of Compression Algorithms for Program Data by Matthew Simpson, Surupa Biswas and Rajeev Barua. Technical report, University of Maryland, College Park, MD. August 2003. 2) Addressing Partitioned Arrays in Distributed Memory Multiprocessors - the Software Virtual Memory Approach. o Rajeev Barua, David Kranz and Anant Agarwal. Proceedings of the MIT Student Workshop, Wellesley, MA, July 1995. ( two-page workshop version) Book Chapters: 1) Optimal Tiling for Minimizing Communication in Distributed Shared-Memory Multiprocessors. o by Anant Agarwal, David Kranz, Rajeev Barua and Venkat Natarajan. Chapter 9, Compiler Optimizations for Scalable Parallel Systems -- Languages, Compilation Techniques and Runtime Systems, LNCS Series 1808, Springer-Verlag, Berlin, Germany, 2001. 2) Dynamic Functional Unit Assignment for Low Power. By S. Haga, N. Reeves and R. Barua. In Embedded Software for SoCs, Kluwer Academic Publishers, Dordrecht, The Netherlands, 2003. My Theses: 1) Maps: A Compiler-Managed Memory System for Software-Exposed Architectures. o by Rajeev Barua, Ph.D thesis, MIT Laboratory for Computer Science, Jan 2000. Available as Technical Report MIT-LCS-TR-799. 2) Global Partitioning of Parallel Loops and Data for Caches and Distributed Memory in Multiprocessors. o by Rajeev Barua. Masters Thesis, MIT Laboratory for Computer Science, May 1994. MIT-LCS-TR-630. Also appears in MIT student workshop, Cape Cod, July 1994. ( two-page workshop version )