ENEE350-Lecture 9

ENEE350
Computer Organization
Lecture-10
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Microprogramming-Overview (microcontroller, VESP-micro-level datapath)

Machine Layer of Vesp

Micro Layer of Vesp

Microcontroller of Vesp

Microprogramming Datapath

Microinstruction formats

Microinstruction bits 0,1

Micro-operation type

00

Data transfer

01

Branch

10

I/O

11

ROM Transfer

Data transfer microinstruction format: 1st row indicates the bit position, 2nd row specifies the field definitions

0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
0	0	A-bus select			B-bus select			Function select				Destination select

Branch microinstruction format: 1st row indicates the bit position, 2nd row specifies the field definitions

0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
0	1	Branch select				Branch address

Microprogrammed I/O: 1st row indicates the bit position, 2nd row specifies the field definitions

0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
1	0	I/O Routine selecr				I/O Routine address

Microstore Transfer: 1st row indicates the bit position, 2nd row specifies the field definitions

0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
1	1	R/W	Read/Write address[13]

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Vesp's microcontroller serves as a mechanism to implement data transfers, branch statements, I/O operations in Vesp and ROM transfers for loading constants in microprograms. Microprogramming-Continued (Microcontroller-or Microsequencer) int microsequencer(void)-Microprogram version { while(1) { /* Step 1: Read the next microinstruction into MIR */ vesp_micro.MAR = vesp_micro.PC; vesp_micro.PC = vesp_micro.PC + 1; vesp_micro.MIR = vesp_micro.MEMORY[vesp_micro.MAR]; /* Step 2: Decode and execute the microinstruction */ switch(vesp_micro.MIR & 0xC0000000) { case 0x00000000: /* µ-operation */

switch(vesp_micro.MIR & 0x38000000) /* ABUS select */

{

case 0x00000000: datapath.ABUS = 0; break;

case 0x08000000: datapath.ABUS = vesp.MEMORY[0]; break;

case 0x10000000: datapath.ABUS = vesp.PC; break;

case 0x18000000: datapath.ABUS = vesp.IR; break;

}

switch(vesp_micro.MIR & 0x07000000) /* BBUS select */

{

case 0x00000000: datapath.BBUS = vesp.MDR; break;

case 0x01000000: datapath.BBUS = vesp.MAR; break;

case 0x02000000: datapath.BBUS = vesp.MEMORY[1]; break;

case 0x03000000: datapath.BBUS = 1; break;

}

switch(vesp_micro.MIR & 0x00F00000) /* Function select */

{

case 0x00000000: datapath.OBUS = datapath.ABUS; break;

case 0x00100000: datapath.OBUS = datapath.ABUS + datapath.BBUS; break;

case 0x00200000: datapath.OBUS = datapath.BBUS; break;

case 0x00300000: break;

case 0x00400000: break;

case 0x00500000: break;

case 0x00600000: break;

case 0x00700000: break;

case 0x00800000: break;

case 0x00900000: break;

case 0x00A00000: break;

case 0x00B00000: break;

case 0x00C00000: break;

case 0x00D00000: break;

case 0x00E00000: break;

case 0x00F00000: break;

}

break; case 0x40000000: /* Branch microinstruction */

switch(vesp_micro.MIR & 0x0000E000)

{

case 0x00000000:

/* branch if A is positive and true branch */

if(vesp.S == 0 && vesp.Z != 1 && (vesp_micro.MIR & 0x00001000) == 0x00001000

||

!(vesp.S == 0 && vesp.Z != 1) && (vesp_micro.MIR & 0x00001000) == 0x00000000)

vesp_micro.MAR = 0x00000FFF & vesp_micro.MIR;

else vesp_micro.MAR = vesp_micro.MAR + 1;

break;

case 0x00001000:

/* branch if A is negative */

if(vesp.S == 1 && (vesp_micro.MIR & 0x00001000) == 0x00001000

vesp.S != 1 && (vesp_micro.MIR & 0x00001000) == 0x00000000)

vesp_micro.MAR = 0x00000FFF & vesp_micro.MIR;

else vesp_micro.MAR = vesp_micro.MAR + 1;

break;

case 0x00002000:

/* branch if A is 0 */

if(vesp.Z == 1 && (vesp_micro.MIR & 0x00001000) == 0x00001000

vesp.Z != 1 && (vesp_micro.MIR & 0x00001000) == 0x00000000)

vesp_micro.MAR = 0x00000FFF & vesp_micro.MIR;

else vesp_micro.MAR = vesp_micro.MAR + 1;

break;

case 0x00003000: break; /* other */

case 0x00004000: break; /* other */

case 0x00005000: break; /* other */

case 0x00006000:

/* always branch */

if ( (vesp_micro.MIR & 0x00001000) == 0x00001000)

vesp_micro.MAR = 0x00000FFF & vesp_micro.MIR;

else vesp_micro.MAR = vesp_micro.MAR + 1;

break;

case 0x00007000: return 1; /* exit */

}

break;

case 0x80000000: /* Input/Output */

switch (vesp_micro.MIR & 0x38000000)

{case 0x00000000: datapath.read = 1; break;

/* More cases */

}

break;

case 0xC0000000: break; /* ROM Transfer */

}

} /* Microcode for fetch Microcode for MAR = PC (0000 => OBUS = ABUS) 00 010 ---- 0000 0100 ---- ------------ Microcode for PC = PC+1 (0001 => OBUS = ABUS + BBUS) 00 010 011 0001 0010 ---- ------------ Microcode for read (000 => read = 1) 10 000 --- ---- ---- ---- ------------ Microcode for IR = MDR (010 => OBUS = BBUS) 00 --- 011 0010 0010 ---- ------------ Microcode for return 01 --- --- ---- ---- 0111 ------------ */

}

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