Advanced Embedded Passives Program

[Introduction] | [Cost Trade Offs] | [Publications]

Introduction

Passive devices (primarily resistors and capacitors) are tiny circuit elements that play a critical role in electronic products. While a portable phone, for example, may have a handful of integrated circuits, it will typically have several hundred passive devices. These devices account for up to 90 percent of the component placements required in the manufacturing process and take up to 40 percent of the space on the printed wiring board (PWB). Embedding these devices into the PWB will increase product density (enabling smaller size, greater performance and higher speeds) and simplify the board assembly manufacturing process.

A group of industrial partners have formed the Advanced Embedded Passives Technology Consortium to manage and execute a NIST ATP project focused on developing the materials, design, and processing technology for embedding passive devices onto circuit board substrates. NCMS and ITRI, and a broad array of industrial partners: 3M, Cadence, Compaq Computer, Delphi Delco Electronics, DuPont Photopolymer & Electronic Materials, DuPont High Performance Films, ESI, MacDermid, Merix Corporation, MicroFab, Nortel Networks, Foresight Systems (formerly Nu Thena Systems), and ORMET Corporation are participating in the program.

The goal of the program is to develop the technology and manufacturing expertise needed to:

• Meet the needs of the microelectronics industry for compact, high-performance products that incorporate proven embedded passives technology
• Lower system costs
• Develop optimum pathways for commercialization of the technology created in the project.

NCMS Press Release

The University of Maryland is the Cost Analysis lead for the program and will perform all cost modeling activities within the program.  The specific objectives of the University of Maryland work are:

• Develop and apply detailed cost models for fabricating substrates with embedded passives
• Compare the economics of applications implemented with discrete passives to implementations using embedded passives.

Cost Trade Offs

There are many drivers pushing system implementations toward the use of embedded passive components. These system drivers include: size/weight reduction, electrical performance, and potentially cost. It is unclear whether, or under what circumstances, system costs can be decreased through the use of embedded passives. Irregardless of why an application may be interested in considering embedded passives, the economics of their use must be understood.

Modeling system costs associated with embedded passives requires consideration of the following technology elements:

• Substrate fabrication costs - the cost (per unit area) of fabricating a substrate (ceramic, laminate, or thin film) will increase when embedded passives are included; the question is how much? Not only does the cost of actually fabricating the substrate increase, but the volume of waste generated during the fabrication process increases as well. With conventional PWBs, waste disposition already comprises 10-15% of the board cost, what is the added waste disposition cost when embedded passives are used?

• Substrate yields - the yield of fabricating substrates that include embedded passives will drop. How much will yield degradation add to the cost of a substrate?

• Substrate area - the area of the substrate will presumably decrease when embedded passives are used. Depending on panelization effects, this area decrease will potentially decrease the substrate cost.

• Assembly costs - the cost of assembling a system will decrease (fewer placements)

• Assembly yields - the yield of assembling a system will increase (fewer connections).

• Test and rework costs - test costs may not change, however, defects associated with embedded passives may not be repairable.

• Trimming costs - depending on the application, design of the circuit, and the embedded passive technology used, some or all embedded passives may have to be trimmed (tuned) to required design values. 

• Discrete passive costs - comparison requires an understanding of discrete, integrated, and array passive component costs.

To properly model the economics of using embedded passives, all these elements must be simultaneously considered.  The modeling work in this program is being addressed in two different tools: 1) the SavanSys software tool from Foresight Systems where the modeling methodology used is the material-centric substrate fabrication process modeling developed within the DARPA "Revo" program, and 2) a first-order standalone model for size/cost tradeoffs that has the following structure and is available at the links below, 

Embedded Passives Cost Modeling Tool (CALCE Members and NIST AEPT Members Only - password required)
Embedded Passives Cost Modeling Tool Public Description and Walkthrough
- This model provides an application-specific economic analysis of the conversion of discrete passive components (resistors and capacitors) to integral passives that are embedded within a printed circuit board. The model performs three basic analyses: 1) Board size analysis is used to determine board sizes, layer counts, and the number of boards that can be fabricated on a panel; 2) Panel fabrication cost modeling including a cost of ownership model is used to determine the impact of throughput changes associated with fabricating integral passive panels; and 3) Assembly modeling is used to determine the cost of assembling all discrete components, and their associated inspection and rework.

Although many references include cost estimates, very few actually address cost modeling and cost tradeoffs for embedded passives.  The following are the known publicly available references:

• J. Rector, “Economic and technical viability of integral passives,” in Proc. Electronic Components and Technology Conference, Seattle, WA, May 1998, pp. 218-224.

• D. Brown, “The economics of integrated passive component technologies - An Ongoing Exploration of a Life Cycle Cost Analysis,” Advancing Microelectronics, vol. 25, no. 3, 1998, pp. 55-58.

• “Ohmega-Ply^â cost analysis,” a white paper available from Ohmega Technologies, Inc., Culver City, CA, www.ohmega.com.

• M. Realff and C. Power, “Technical cost modeling for decisions in integrated vs. surface mount passives,” in Proc. IMAPS 3^rd Advanced Technology Workshop on Integrated Passives Technology, Denver, CO, April 1998.

• C. Power, M. Realff, and S. Battacharya, “A decision tool for design of manufacturing systems for integrated passive substrates,” in Proc. IMAPS 4^th Advanced Technology Workshop on Integrated Passives Technology, Denver, CO, April 1999.

• M. Scheffler, G. Troster, J. L. Contreras, J. Hartung, and M. Menard, "Assessing the cost-effectiveness of integral passives," Microelectronics International, vol. 17, no. 3, 2000, pp. 11-15.

• P. A. Sandborn, B. Etienne, and G. Subramanian, “Application-Specific Economic Analysis of Integral Passives,” IEEE Trans. on Electronics Packaging Manufacturing, Vol. 24, No. 3, pp. 203-213, July 2001.

• P. Sandborn, "The Economics of Embedded Passives," in Integrated Passive Component Technology, R. Ulrich and L. Schaper editors, IEEE Press, 2003.

Publications Related to this Program

P. Sandborn and P. A. Sandborn, “A Random Trimming Approach for Obtaining High-Precision Embedded Resistors,” IEEE Trans. on Advanced Packaging, Vol. 31, No. 1, pp. 76-81, February 2008.

B. Etienne and P. Sandborn, "Optimizing Embedded Passive Content in Printed Circuit Boards," IEEE Trans. on Electronics Packaging Manufacturing, Vol. 30, No. 4, pp. 246-257, October 2007.

L.J. Salzano II, C. Wilkinson, and P.A. Sandborn, "Environmental Qualification Testing and Failure Analysis of Embedded Resistors," IEEE Trans. on Advanced Packaging, Vol. 28, No. 3, pp. 503-520, August 2005.

P. Sandborn, “An Assessment of Embedded Resistor Trimming and Rework,” IEEE Trans. on Electronics Packaging Manufacturing, Vol. 28, No. 2, pp. 176-186, April 2005.

P. Sandborn, "The Economics of Embedded Passives," in Integrated Passive Component Technology, R. Ulrich and L. Schaper editors, IEEE Press, 2003.

P. Sandborn, "The Economics of Embedded Passives," to be published Proceedings of InterPACK, Summer 2003.

"Cutting Costs, and Circuit Boards, Down to Size," Maryland Research Magazine, p. 4, Fall, 2002.