References

 

[1]���� C.H. Stapper, �The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions,� IBM J. Res. Develop., vol. 29, no. 1, pp. 87-97, Jan. 1985.��������

 

[2]���� A. V. Ferris-Prabhu, �Modeling the critical area in yield forecasts,� IEEE J. Solid-State Circuits, vol. SC-20, no. 4, pp. 874-878, Aug. 1985.

 

[3]���� C.H. Stapper, �Modeling of defects in integrated circuit photolithographic patterns,� IBM J. Res. Develop., vol. 28, no. 4, pp. 461-474, July 1984.

 

[4]���� R. M. Warner Jr., �Applying a composite model to the IC yield problem,� IEEE J. Solid-State Circuits, vol. SC-9, no. 3, pp. 86-95, June 1974.

 

[5]���� B. T. Murphy, �Cost-size optima of monolithic integrated circuits,� in Proc. IEEE, Dec. 1964, pp. 1537-1545.

 

[6]���� C. H. Stapper, �The defect-sensitivity effect of memory chips,� IEEE J. Solid-State Circuits, vol. SC-21, no. 1, pp. 193-198, Feb. 1986.

 

[7]���� C. H. Stapper, �Yield statistics for large area IC�s,� in IEEE Int. Solid-State Circuits Conf. Digest of Technical Papers Rec., pp. 168-169, Feb. 1986.

 

[8]���� A. B. Glaser and G. E. Subak-Sharpe, Integrated Circuit Engineering.Reading, MA: Addison-Wesley, 1979. chap. 16.

 

[9]���� CRC Standard Math Tables, 12th Edition, Chemical Rubber Publishing Co., 1961, p. 317.

 

[10]��� M. B. Ketchen, �Point defect yield model for wafer scale integration,� IEEE Circuits and Devices, vol. 1, no. 4, pp. 24-34, July 1985.

 

[11]��� T. L. Michalka, et al, �A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy,� IEEE Trans. On Semicondutor Manufacturing. Vol. 3, no. 3, pp. 116-127, Aug. 1990 **

 

**����� This project is completely based on this paper.