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University of Maryland -
http://www.ece.umd.edu/~blj/
Current ultra-high-performance computers execute instructions at the rate of roughly 10 PFLOPS (10 quadrillion floating-point operations per second) and dissipate power in the range of 10 MW. The next generation will need to execute instructions at EFLOPS rates -- 100x as fast as today's -- but without dissipating any more power. To achieve this challenging goal, the emphasis is on power-efficient execution. Energy and power costs are the primary reasons that our system-wide execution throughput (OPS) is no better than it currently is -- while one could staple together 100 supercomputers to create an exascale system, not many could afford to pay the resulting electric bill. And yet, a significant amount of research is still focused on increasing processor performance, rather than decreasing power and energy-to-solution. Modern high-performance systems are not throughput-bound; they are power-bound. Processing is so cheap it is effectively free; shaving power and energy costs at every opportunity, and at every level of the system, is the trick. Similarly, memory and communication are the primary reasons that our time-to-solution is no better than it currently is -- the memory system is slow; the communication overhead is high; and yet a significant amount of research is still focused on increasing processor performance, rather than decreasing (the cost of) data movement. Modern high-performance systems are not compute-bound; they are data-bound. ALUs are so cheap that some propose to put them out in the memory -- processing is free; getting the right data to the right place, cheaply, is the trick. This page describes our work in high-performance systems, including flash-based main memories and Micron's Hybrid Memory Cube DRAM, as well as our current multiprocessor system-design work.
Brought to you by Northrop Grumman, Intel, Micron, Sandia National Labs, US Dept. of Energy, and No Such Agency |
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| 2014 | SAMOS Keynote |
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| 2013 | FORTH |
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