Research Interests
- On-Chip Interconnection Networks
- High Performance Digital Circuits
- Parallel Computing
Ph.D. Dissertation Title:
Mesh-of-Trees Interconnection Network for an Explicit Multi-Threaded
Parallel Computer Architecture (August, 2008)
Mesh-of-Trees Interconnection Network Chip Die Photos
We fabricated 8-Terminal Mesh-of-Trees Interconnection Network with
dummy terminals. In a real design, processors and memory
modules will replace these terminals.
Short List of Specs
- The chips were fabricated at IBM 90nm technology (9SF).
- ARM standard cell libraries are used.
- Die size is 9mm x 5mm (width x height)
- Designed and sent to foundry in March 2007.
- Bare dies arrived in August 2007.
- A Xilinx Virtex-II Pro development board is used for
testing. FPGA is configured to stimulate the network chip and record
the output.
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Publications
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Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism
A. O. Balkan, G. Qu, U. Vishkin;
IEEE Transactions on Very Large Scale Integration Systems (TVLSI); accepted June 2008; to appear
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An Area-Efficient High-Throughput Hybrid Interconnection Network
for Single-Chip Parallel Processing
A. O. Balkan, G. Qu, U. Vishkin;
IEEE 45th Design Automation Conference (DAC); June 2008; Anaheim, CA
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Layout-Accurate Design and Implementation of a High-Throughput
Interconnection Network for Single-Chip Parallel Processing
A. O. Balkan, M. N. Horak, G. Qu, U. Vishkin;
IEEE 15th
International Symposium on High-Performance Interconnects (Hot
Interconnects, HOTI); August 2007; Stanford University
pdf
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A Mesh-of-Trees Interconnection Network for Single Chip Parallelism
A. O. Balkan, G. Qu, U. Vishkin;
IEEE 17th International Conference
on Application-specific Systems, Architectures and Processors
(ASAP); September 2006; Steamboat Springs, CO
Best Paper Award
Slide show
Permanent Link
pdf
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Arbitrate-and-Move Primitives for
High-Throughput On-Chip Interconnection Networks
A. O. Balkan, G. Qu, U. Vishkin;
IEEE International
Symposium on Circuits and Systems (ISCAS); May 2004; Vancouver BC,
Canada
Permanent Link
pdf
Other Papers and Technical Reports
-
Programmer's Manual for XMTC Language, XMTC Compiler and XMT
Simulator
A. Balkan, U. Vishkin, G. C. Caragea, A. Tzannes;
Used as supplementary text for programming assignments of following
courses and tutorials:
- ENEE759K/CMSC751: Parallel Algorithmics (University of
Maryland - College Park)
- ENEE459P/CMSC498V: Parallel Algorithms (University of
Maryland - College Park, Spring 2008)
- HONR219A: Towards a New Era of Desktop Supercomputing
(University of Maryland - College Park, Spring 2008)
- Tutorial on "How to Think Algorithmically in Parallel", Seattle,
WA, Sunday, June 17, 2007, held in conjunction with the 21st ACM
International Conference on Supercomputing (ICS).
- On-Line
Tutorial on Parallel Programming through Parallel
Algorithms
Initial (older) version is available as Technical Report UMIACS-TR 2005-45
Permanent Link
This document is evloving with the advances in XMT computing
platform, and XMT tools such as compiler and simulator.
Currently, it is maintained by G. C. Caragea and
A. Tzannes. Most recent version is available at
XMT Project
Home Page as XMTC Manual and XMTC Tutorial
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Mesh-of-Trees and Alternative Interconnection Networks for
Single Chip Parallel Processing (Extended Abstract)
A. Balkan, G. Qu, U. Vishkin;
Technical Report UMIACS-TR 2006-32
Permanent Link
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Coordinating Pricing and Capacity Decisions in Service
Networks
G. Gurkan, I. Karaesmen, B. Deniz and A. Balkan;
A preliminary version presented at INFORMS
Annual Meeting in San Francisco 2005 (presented by I. Karaesmen)
Technical Talks and Presentations
-
PRAM-on-Chip : Vertical Design of an Easy-to-Program General
Purpose Parallel Processor
Design Automation Conference (DAC) University Booth, June 9-12,
2008
(This project and presentation contains valuable contributions
from the
XMT
Team. A list of the contributors is available at
the at XMT
Project Home Page.)
-
Gate/Transistor Level Design, Simulation and Optimization of
Digital Circuits Using Cadence Tools,
ECE Graduate Student Seminar Series, University of Maryland,
March 12, 2004
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Contact
balkanay "at" umd "dot" edu
A.V. Williams Bldg. Room 3444
University of Maryland
College Park, MD 20742
You can also contact me at
Links
XMT Project
"A Desktop Supercomputer" Home Page
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